| 1. |
Supports independent Add and Drop Bus timing and operating modes |
| 2. |
High-order or low-order pointers are processed and monitored including Loss Of Pointer (LOP-P), New Data Flags (NDF), and Alarm Indication Signal (AIS-P) |
| 3. |
High-speed microprocessor interface is configurable to operate with most commercial 16 bits microprocessors |
| 4. |
Low power CMOS technology with 1.8V core and 3.3V I/O and boundary scan |
| 5. |
Easy for configuration and programming for software development. (specification was defined to ease and speed up the software development) |
| 6. |
Unique Dual Telecom Bus Timing Interface |
| 7. |
Independently programmable Add/Drop TU/VT time slot |
| 8. |
Protection Switch Recovery Time from East to West is below 10 ms |
| 9. |
Full Bandwidth of STM-1 Support :Totally 3xVC3/63xVC12/84xVC11 (64VC11/perVCG) |
| 10. |
Mix of High Order (HO) and Low Order (LO) Mapping into STM-1 |
| 11. |
Up To 255 ms Differential Delay Compensation |
| 12. |
Latency Below ~ 200uS (LO) |
| 13. |
Optional size of SDRAM support (64Mb/128Mb/256Mb) |
| 14. |
Support SDRAM interface test-mode which effectively help initial debugging to reduce the development cycle |
| 15. |
Optional Grace mode function for Drop-side FIFO control |
| 16. |
Efficient software and hardware technical support |
