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Chips
    DS1FR
    P1M8
    P1M16
    P3M3
    P3M1
    EOSM4
    EOSM155
    EOPM4
    EOPM8
    EOPM84
    EODS3
    VLM155S
    VLM155
    XC4
    XC16
    CDR155G(LQFP-32)
    CDR155G-H (LQFP-32)
    CDR155G-H (SOP-28)
    DOHP155T-676
    DOHP155T-320
    DOHP155T-ADM
    MTUP(PQFP-160)
    MTUP (LQFP-128)
    MUX155 (Green Package)

SFP Module
    SFP-101
    SFP-102
    SFP-111
    SFP-112
    SFP-113


Overview
Dual SDH STM-1 Overhead Processor
DOHP155T-ADM (GC98159A-DS)

    The DOHP155T is a monolithic integrated circuit that processes the section overhead of STM-1 streams at up to 155.52 Mb/s and implements payload alignment and path termination for VC-4 payload.
    The DOHP155T receives dual SDH STM-1 frames via a bit serial interface and it processes dual regenerator section overhead and APS bytes (K1, K2). It support 1+1 MSP protection. Only the “multiplexer section” overhead on the selected STM-1 data stream is processed. On the outgoing STM-1 stream, the STM-1 data excluded REG Overhead, K1/K2 and B2 are duplicated. It performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors regenerator section and multiplex section bit interleaved parity (B1, B2), accumulating error counts at each level for performance monitoring purposes. Multiplex section far end block error (REI) indications (M1) are also monitored. A 1, 16 bytes section trace (J0) sequence may be processed.
    The DOHP155T transmits SDH STM-1 frames, via a bit-serial interface, and formats regenerator section and multiplex section overhead appropriately. It performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates regenerator section and multiplex section bit interleaved parity (B1, B2) as required to allow performance monitoring at the far end.
    Multiplex section far end block error (REI) indications (M1) are also inserted. A 1, 16 bytes section trace (J0) sequence may be inserted.
    The DOHP155T generates the transmit payload pointers (H1, H2) and inserts the synchronous payload envelope (virtual container) from an ADD bus or data interface in the transmission stream. Frequency offsets and phase differences between the transmission data stream and the ADD bus are accommodated by pointer adjustments in the transmission stream.
    The DOHP155T can be programmed to pass part or all of the path overhead byte on the ADD bus through unaltered.
    The transmitter and receiver are independently configurable to allow for different reference timing interfaces. The DOHP155T is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.


Key Features
 
1.
SDH STM-1 TOH and POH processor
2.
Support dual STM-1 framer and dual REG overhead processing for 1+1 MSP protection
3.
Operates at 155.52 MHz bit serial of 155.52 Mbits/s data stream
4.
Supports dual Telecom bus to interface with GCI’s VLM155, P1M8 and P3M3 Mappers

Product Applications
 
1.
SDH add/drop multiplexer
2.
SDH path terminal multiplexer
3.
SDH cross connect system
4.
SDH test equipment
5.
Broadband Access Node

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